View ISL6247_7796728.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly fn9113 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved.. all other trademarks mentioned are the property of their respective owners. confidential ISL6247 a mobile multi-phase pwm controller with precision current sensing the ISL6247 provides microprocessor core-voltage regulation by driving up to four interleaved synchronous- rectified buck-converter channels in parallel. multi-phase buck converter architecture uses interleaved timing to multiply ripple frequency and reduce input and output ripple currents. the reduction in ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. the ISL6247 multi-phase controller together with isl6207 gate drivers forms the basis for a portable power supply solution to power intel?s next generation mobile microprocessors. intel mobile voltage positioning (imvp) is a smart voltage regulation technology which effectively reduces power dissipation in intel ? pentium ? processors. the ISL6247 supports the imvp-5 mobile processor voltage regulation specifications. to boost battery life, the ISL6247 operates in active, deep sleep, or deeper sleep modes, depending upon the logic levels at the dsen# and drsen pins. a 6-bit digital-to-analog converter (dac) allows dynamic adjustment of the core output voltage from 0.8375v to 1.6v. the controller features a thermal monitor which sends a signal to the microprocessor to reduce the load before power system components exceed their maximum thermal limits, reducing the thermal design complexity and overall core-voltage regulation cost. to improve efficiency, the ISL6247 allows users to select one of two popular lossless current sense techniques. the ISL6247 supports detection via inductor coil resistance (dcr), or the r ds(on) of the lower mosfet. either cost and space-saving method provides feedback for precision droop, channel current balancing, and individual channel over-current protection. a unity gain, differential amplifier is provided for remote voltage sensing. the differential amplifier eliminates errors due to potential differences between remote and local grounds. eliminating ground differences improves regulation and protection accuracy. the channel switching frequency is adjustable in the range of 200khz to 1.0mhz, providing flexibility in managing the balance between high-speed response, target efficiency, and good thermal management. features ? precision multi-phase core voltage regulation - 0.6% system accuracy over temperature ? microprocessor voltage identification input - 6-bit vid input - 0.8375v to 1.600v in 12.5mv steps - supports vid changes during operation ? multiple current sensing approaches supported - lossless dcr current sensing - precision resistive current sensing -low cost r ds(on) current sensing ? excellent dynamic response - combined input voltage feed-forward and pulse-by- pulse average current mode ? dsen# and drsen logic inputs for low power states ? dsv voltage input for deep sleep mode ? drsv voltage input for deeper sleep mode ? thermal monitor ? active channel current balancing ? differential remote voltage sensing ? individual channel over-current, over-voltage, and under-voltage protection ? 2, 3, or 4-phase operation ? user selectable switching frequency of 200k - 1.0mhz - 400khz - 4mhz effective ripple frequency ? qfn package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile applications ? notebook computer imvp-5 dc/dc converter pinout ISL6247cr (40 ld qfn 6x6) top view ordering information part number temp. ( o c) package pkg. dwg. # ISL6247cr -10 to 100 40 ld 6x6 qfn l40.6x6 ISL6247cr-t 40 lead 6x6 qfn tape and reel lead-free packaging (pb free) ISL6247crz -10 to 100 40 ld 6x6 qfn l40.6x6 ISL6247crz-t 40 lead 6x6 qfn tape and reel vid4 vid3 vid2 vid1 rampadj isen1- vid5 pwm1 vrtn vid0 gnd comp fb vdiff vsen pwm2 pwm3 isen1+ dsv ocset ofs enll fs drsen drsv vcc pwm4 pgood vr-tt# gnd nc isen3+ isen3- isen2- isen2+ isen4+ isen4- soft dsen# ntc 40 gnd pad [bottom] 39 38 37 36 35 34 32 33 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 data sheet june 2003
2 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v input, output, or i/o voltage . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . -10 o c to 100 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . -10 o c to 125 o c thermal information thermal resistance (typical, note 1) ja ( o c/w) ja ( o c/w) qfn package . . . . . . . . . . . . . . . . . 32 3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 2. jc , the ?case temperature? location is t he center of the exposed metal pad on the pack age underside. see tech brief tb379 for det ails. electrical specifications operating conditions: vcc = 5v, t a = -10 o c to 85 o c. unless otherwise specified. parameter test conditions min typ max units input supply power operating current r fs = 90.9k ; enll = 1v - 12 17 ma shutdown current r fs = gnd; enll = 0v - 12 17 ma por (power-on reset) threshold vcc rising; fb = 0v 4.20 4.35 4.50 v vcc falling; fb = 0v 3.65 3.80 3.95 v enable input (enll) enable threshold 0.5 0.6 0.7 v high state leakage current enll = 1.0v - -200 - na low state leakage current enll = 0.0v - 49 - a reference voltage and dac system accuracy 25oc -0.5 - +0.5 %vid v dac = 1.1000v to 1.6000v -0.6 - +0.6 %vid v dac = 0.8375v to 1.0875v -0.7 - +0.7 %vid vid input threshold voltage 0.4 0.6 0.8 v vid current vid x = 0.0v - 47 - a vid x = 1.0v 0 -1.5 -10 a oscillator accuracy r fs = 90.9k ? 1% 270 300 330 khz adjustment range 200 1000 khz sawtooth ramp amplitude v rampadj = 1.8v - 1.0 - v duty-cycle range 0-66% fs output voltage r fs = 90.9k ? 1% 1.223 1.235 1.247 v error amplifier open-loop gain r l = 10k ? to ground - 72 - db open-loop bandwidth c l = 100pf, r l = 10k ? to ground - 18 - mhz slew rate c l = 100pf, r l = 10k ? to ground - 5.3 - v/ s maximum output voltage fb = gnd; v dac = 1.1v; r l = 10k ? to ground 3.6 4.2 - v minimum output voltage fb = 1.2; v dac = 1.1v; sinking 300 a-0.2-v output sourcing current vcomp = 2v; fb = 0.75v; v dac = 1v 0.82 2.1 - ma output sinking current vcomp = 1v; fb = 1.25; v dac = 1v 1.2 1.6 - ma input offset fb = 1v; ofs = open - 0 - mv ISL6247
3 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly note: differential and error amp of offsets are trimmed out for system accuracy. pin-adjustable offset ofs voltage i ofs = -20 a; respect to gnd - 0.5 - v i ofs = 20 a; respect to v cc --2- v pwm pwm high state i pwm = -2.5ma - 4.5 - v pwm low state i pwm = +5ma - 0.7 - v pwm three-state pwm = 2.5v -1 - 1 a differential sense amplifier bandwidth -20-mhz slew rate -6-v/ s input offset vsen = 1.6v; vrtn = 0.005v; - 2 - mv input bias current vsen = 1.2v -100 - 100 na pull-down current vsen = 0.6v; vdiff = 0.7v - 800 - a output impedance -30- ? current sense amplifiers input offset [(isen+) - (isen-)] -5 - 5 mv i sen accuracy isen1=isen2=isen3=isen4=50 a-8-8% soft start initial soft-start current soft < 0.5v - 25 - a soft slew current soft > 0.5v - 500 - a deeper sleep slew current (entering only) s oft = 1v; dsen = 0v; drsen = 2v - 100 - a power good and protection monitors pgood low voltage i pgood = -4ma; enll = gnd - 0.18 0.40 v pgood leakage current pgood = 5v -1 0 1 a under-voltage threshold vsen rising - 90 - %vid vsen falling 84 86 88 %vid over-voltage threshold (vid + ov threshold) 170 200 230 mv ocset voltage accuracy v dac = 1.325v - 1.325 - v i sen over-current trip level r ocset = 13.25k ?; v dac = 1.325v - -77 - a input leakage current fb isen1=isen2=isen3=isen4 = 0 a; ofs open - 50 - na dsv, drsv -50- na rampadj ramadj = 1.8v - 100 - na sleep state thresholds deep sleep enable threshold dsen# rising 1.7 - - v dsen# falling - - 1.05 v deeper sleep enable threshold drsen rising 1.7 - - v drsen falling - - 1.05 v deep and deeper sleep voltage dsv accuracy (v out - dsv); dsv = 1.2v -15 - +15 mv drsv accuracy (v out - drsv); drsv = 0.75v -15 - +15 mv thermal monitor ntc source current ntc = 0.6v 34 40 47 a over-temperature threshold v (ntc) falling 0.485 0.5 0.525 v vr-tt# on-resistance ntc < 0.5v; vr-tt# = -4ma; t a = 25 o c-12- ? vr-tt# sinking current vr-tt# voltage = 0.2v;t a = 85 o c13-17.5ma electrical specifications operating conditions: vcc = 5v, t a = -10 o c to 85 o c. unless otherwise specified. (continued) parameter test conditions min typ max units ISL6247
4 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly typical operating performance figure 1. active load line figure 2. deep sleep load line figure 3. deeper sleep load line figure 4. active efficiency figure 5. deep sleep efficiency figure 6. deeper sleep efficiency ISL6247 active mode load line 1.19 1.21 1.23 1.25 1.27 1.29 1.31 1.33 1.35 0 1020304050607080 output current (a) output voltage (v) vmax vmin vnom vin = 19v vin = 10.8v output current (a) output voltage (v) ISL6247 active mode load line ISL6247 deep sleep load line 1.24 1.25 1.26 1.27 1.28 1.29 1.3 1.31 1.32 1.33 1.34 0 5 10 15 20 25 output current output voltage vmax vmin vnom vin=19v vin = 10.8v output current output voltage ISL6247 deep sleep load line ISL6247 deeper sleep load line 0.74 0.75 0.76 0.77 0.78 0.79 0.8 0.81 0.82 0.83 0.84 0.85 012345678 output current output voltage vmax vmin vnom vin =19v vin =10.8v output current output voltage ISL6247 deeper sleep load line ISL6247 active mode efficiency 50.00% 60.00% 70.00% 80.00% 90.00% 100.00% 0 1020304050607080 output current efficiency vin = 19v vin = 14.4v vin = 10.8v vin = 8.4v output current efficiency ISL6247 active mode efficiency ISL6247 deep sleep efficiency 50.00% 60.00% 70.00% 80.00% 90.00% 100.00% 0 5 10 15 20 25 output current efficiency vin = 19v vin = 14.4v vin = 10.8v vin = 8.4v output current efficiency ISL6247 deep sleep efficiency ISL6247 deeper sleep efficiency 50.00% 60.00% 70.00% 80.00% 90.00% 100.00% 012345678 output current efficiency vin = 19v vin = 14.4v vin = 10.8v vin = 8.4v output current efficiency ISL6247 deeper sleep efficiency ISL6247
5 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly figure 7. soft start waveform figure 8. inrush current at vin 10.8v @ 80a figure 9. inrush current at vin 19v @ 80a figure 10. four phase current balance @ 80a figure 11. three phase current balance @ 60a figure 12. vid change from 1.350v to 1.150v ISL6247
6 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly figure 13. transient waveform from 0a to 80a figure 14. geyserville transition figure 15. active to deep sleep transition figure 16. inductor current transient figure 17. c4 transition figure 18. ds to drs transition ISL6247
7 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly functional pin description vcc connect a +5v power supply to the vcc pin to supply all the power necessary to operate the controller. when the voltage on this pin exceeds the rising power-on reset (por) threshold, the controller can begin to operate. the controller will shutdown when the voltage on the vcc pin drops below the falling por threshold. gnd the gnd pin is the bias and signal ground for the controller. enll the enll pin is a logic-level enable input to the controller. asserting a logic high (>0.6v), the controller is active, depending on the status of the internal por and fault states. cycling enll to zero will clear all fault states and prime the controller to soft start when re-enabled. enll is 5v capable. fs connect a resistor from fs to ground to program the switching frequency. there is an inverse relationship between the value of the resistor and the switching frequency. the voltage at this pin is held at 1.235v and provides a reference for the deeper sleep voltage (drsv) divider. vid5, vid4, vid3, vid2, vid1, vid0 the state of these six pins program the internal dac, which provides the reference voltage for output regulation. these pins have low current (50 a) internal pull-ups. connect these pins to either open-drain with external pull-up resistors or active-pull-up type outputs. vdiff, vsen, and vrtn vsen and vrtn form the inputs to a differential amplifier. the differential amplifier converts the remotely sensed differential voltage of the regulated output to a single-ended voltage, referenced to the local ground of the controller. vdiff is the amplifier output and the input to the regulation and protection circuitry. connect vsen and vrtn to the sense pins of the remote load. fb and comp fb is the inverting input and comp is the output of the internal error amplifier, respectively. fb is connected to vdiff through an rc network with a dc resistive connection. comp is tied back to fb through an external rc network with no dc connection for compensating the regulator. rampadj voltage on the rampadj pin sets the ramp amplitude, providing feed-forward information to the voltage control loop. this should be set at 1/9th of the battery voltage input with an external resistive divider. ofs the ofs pin provides a programmable means to introduce a dc offset voltage to the dac reference. the offset is generated by an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left open. the current which flows through the resistor is output on the fb pin. the magnitude of the offset is determined by the reference voltage and the ratio of the ofs programming resistor to the dc impedance of vdiff to fb. ofs is intended for introducing offsets in a range within 50mv of the dac setting. pwm1, pwm2, pwm3, pwm4 pwm1, pwm2, pwm3 and pwm4 are pulse-width modulating outputs. these logic outputs instruct the driver ic(s) when to turn-on and turn-off the synchronous buck mosfets of each channel. the number of active channels is determined by the state of pwm3 and pwm4. if pwm3 is tied to vcc, two channel operation is indicated to the controller. in this case, pwm4 should be left open or tied to vcc. shorting pwm4 to vcc indicates that three channel operation is desired. vid4 vid3 vid2 vid1 rampadj isen1- vid5 pwm1 vrtn vid0 gnd comp fb vdiff vsen pwm2 pwm3 isen1+ dsv ocset ofs enll fs drsen drsv vcc pwm4 pgood vr-tt# gnd nc isen3+ isen3- isen2- isen2+ isen4+ isen4- soft dsen# ntc 40 gnd pad [bottom] 39 38 37 36 35 34 32 33 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 ISL6247
8 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly isen1+, isen1-, isen2+, isen2-, isen3+, isen3-, isen4+, isen4- the isen+ and isen- pins are current sense inputs to individual differential amplifiers. for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the sense capacitor through a resistor, r isen . the voltage across the sense capacitor is proportional to the inductor current. the sense current is proportional to the output current, and scaled by the dcr of the inductor, divided by r isen . when configured for r ds(on) current sensing, the isen1-, isen2-, isen3-, and isen4- pins are grounded at the lower mosfet sources. the isen1+, isen2+, isen3+, and isen4+ pins are then held at a virtual ground, such that a resistor connected between them, and the drain terminal of the associated lower mosfet, will carry a current proportional to the current flowing through that channel. the current is determined by the negative voltage developed across the lower mosfet?s r ds(on) , which is the channel current scaled by r ds(on) . the sensed current is used as a reference for channel balancing, over-current protection, and load-line regulation (by way of the fb pin). inactive channels should have their respective sense inputs left open (for example, for 3-phase operation open isen4+). dsen# the dsen# logic-level pin toggles the controller between active and deep sleep modes. when held at logic low and drsen is low, the controller changes to deep sleep mode. the output voltage is set to the voltage on the dsv pin. dsv the voltage on the dsv pin programs the output voltage in deep sleep mode. an external resistor divider from the ocset pin can be used to set this voltage. drsen the drsen pin is a logic-level enable for deeper sleep mode. while dsen# is low, if the drsen pin is pulled high, the controller transitions from deep sleep to deeper sleep mode. the output voltage is set to the voltage on the drsv pin. drsv the voltage on the drsv pin programs the output voltage in deeper sleep mode. an external resistor divider from the fs pin sets the drsv voltage level. soft the soft pin programs the output slew rate for speedstep or mode of operation changes. this pin is connected to ground via a capacitor. vr-tt# the vr-tt# pin is the voltage regulator thermal management signal. vr-tt# is an open-drain, active low output signal. ntc the ntc pin commands the vr-tt# signal low when the voltage of this pin is less than 0.5v. connect this pin to gnd with a negative temperature coefficient (ntc) resistor. a 40 a current source flows out this pin to set the voltage drop across the ntc resistor. ocset the voltage on the ocset pin is the dac voltage. resistors from ocset to gnd set the over-current protection threshold and the deep sleep voltage, dsv, proportional to v dac . pgood the pgood pin is an open drain output and used to indicate the status of the output voltage. pgood is pulled high, through an external pull-up resistor, when the output voltage is within the regulation limits. ISL6247
9 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly typical application: 4-phase buck converter with dcr current sensing vid3 +5v pwm vcc boot ugate phase lgate gnd +5v vin pwm vcc boot ugate phase lgate en gnd vin pwm vcc boot ugate phase lgate en gnd +5v isl6207 driver vin pwm vcc boot ugate phase lgate en gnd +5v isl6207 driver vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc vrtn isen1+ pwm1 pwm2 isen2+ pwm3 isen3+ pwm4 isen4+ ISL6247 p load vid5 isen1- isen2- isen3- isen4- ntc driver isl6207 en driver isl6207 soft ocset dsv ntc dsen# drsen rampadj vin fs drsv vr-tt# gnd ofs +5v gnd +5v c out channel 1 enll ptc ptc ptc ptc channel 2 channel 3 channel 4 1f 0.15f 10nf 820 ? 0.56h 2xsi4362dy 32.4k 2xirf7811w 2xirf7811w 0.15f 1f 0.56h 32.4k 10nf 2xsi4362dy 820 ? 2xirf7811w 0.56h 32.4k 10nf 2xsi4362dy 820 ? 0.15f 1f 2xirf7811w 0.56h 32.4k 10nf 2xsi4362dy 820 ? 0.15f 1f 80.6k 10k 61.9k 30.9k 17.4k 82nf 301 ? dni 316k 1f 1.91 k 16.9k 1.5nf 330k note : do not install = dni ISL6247
10 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly block diagram i ocset channel power-on reset (por) + - e/a + - pwm pwm pwm1 pwm2 pwm3 pwm4 gnd vcc fb fs + - + + - + - pwm + - pwm clock and vid4 vid3 vid2 vid1 comp vsen generator sawtooth isen3+ isen4+ vid0 vrtn enll 0.6v +- + + + + - + - + - i droop ocset vid d/a sample hold & current balance channel select ofs three-state isen1+ isen2+ v dac vid5 soft isen1- isen2- isen3- isen4- vdiff pgood ovp + x1 + - - control and fault logic +200mv rampadj 1.235v soft start v dac or v soft v soft higher - + 90% rising 86% falling 8 count clock cycle uv ntc 0.5v + - 40 a vr-tt# v core ref dsv drsv dsen# drsen mux channel current sense offset three-state three-state three-state channel overcurrent detection 32 count up-down counter x 1.3 ? ISL6247
11 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly theory of operation multi-phase power conversion microprocessor load current profiles have advanced to a point where single-phase converter solutions face arduous thermal and cost hurdles. although its greater complexity presents additional technical challenges, multi-phase power conversion offers cost-saving advantages with improved response time, superior ripple cancellation, and excellent thermal distribution. the ISL6247 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. the block diagram in figure 19 provides a top level view of multi-phase power conversion using the ISL6247 controller. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. in a 4-phase converter, each channel switches 1/4 cycle after the previous channel and 1/4 cycle before the following channel. as a result, the four-phase converter has a combined ripple frequency four times greater than the switching frequency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). the increased ripple frequency and lower ripple amplitude, relative to a single phase approach, results in less per-channel inductance and lower total output capacitance required to meet any performance specification. figure 20 illustrates the multiplicative effect of a 3-channel multiphase converter on output ripple frequency. the three channel currents (il1, il2, and il3), combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to-peak current waveform for each phase is about one division, and the dc components of the inductor currents combine to feed the load. + error amplifier v out q3 q4 l 02 c out v in hip6207 - pwm circuit i droop + - figure 19. simplified block diagram of the ISL6247 in a 2-phase converter with dcr current sensing pwm2 isen2- current sense r sen2 current sense isen1- current balance q2 l 01 hip6207 pwm circuit pwm1 q1 + - 4 --- fb reference mux vid,dsv,drsv comp + - vrtn vsen x1 vdiff r fb r 2 c 3 r 1 c 1 c 2 pwm3 channel detect pwm4 vcc open v comp current isen2+ isen1+ (ptc) r sen1 (ptc) balance correction signal ISL6247
12 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly equation 1 is an individual channel?s peak-to-peak inductor current. where, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitor, c out , conducts the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. equation 2 is the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output-voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is the reduction of input ripple current. figure 21 illustrates input current reduction for a three-phase converter. each channel current, as measured through the drain of the upper mosfet, fills in the input capacitor current. the resulting rms value is less than the input rms current of a single-phase converter, at the same regulator output current. figures 44, 45 and 46, in the section entitled input capacitor selection, can be used to determine the input-capacitor rms current based on load current, duty cycle, and the number of channels. they are provided as aids in determining the optimal input capacitor solution. pwm operation the ISL6247 can operate as a 2, 3, or 4 phase converter. the timing of each converter is determined by the number of active channels. by default, the timing mode for the ISL6247 is 4-phase. select 2-phase timing by connecting pwm3 to vcc and leaving pwm4 open, or by connecting pwm4 to vcc as well. select 3-phase timing by connecting only pwm4 to vcc. one switching cycle is defined as the time between falling pwm1 signals. the cycle time is the inverse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands the channel-1 pwm output to go low. the pwm1 transition signals the channel-1 mosfet driver to turn off the channel- 1 upper mosfet and turn on the channel-1 synchronous mosfet. if two-channel operation is selected, the pwm2 pulse terminates 1/2 of a cycle later. if three channels are selected, the pwm2 pulse terminates 1/3 of a cycle after pwm1, and the pwm3 output will follow after another 1/3 of a cycle. when four channels are selected, the pulse termination times are spaced in 1/4 cycle increments. once a pwm signal transitions low, it is held low for a minimum of 1/3 switching cycle. this forced off-time is required to ensure an accurate current sample, as described in current sampling . once the forced off-time expires, the pwm output is enabled. the pwm output state is driven by the position of the error amplifier output signal v comp , minus the current correction signal relative to the sawtooth ramp, as illustrated in figure 19. for balanced channel current, the current correction signal is zero, and when the sawtooth ramp crosses the modified v comp voltage, the pwm output transitions high. the mosfet driver detects the change in state of the pwm signal, turns off the synchronous mosfet, and turns on the upper mosfet. the pwm signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the pwm signal low. i pp v in v out ? () v out lf s v in ----------------------------------------------------- - = (eq. 1) figure 20. pwm and inductor-current waveforms for 3-phase converter time pwm2 pwm1 il2 il1 il1 + il2 + il3 il3 pwm3 il1 i cpp , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 2) figure 21. channel input currents and input- capacitor current for 3-phase converter time channel 3 current channel 2 current channel 1 current input-capacitor current ISL6247
13 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly current sampling during the forced off-time, following a pwm transition low, the associated channel current sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . no matter the current sense method employed, the sense current (i sen ) is simply a scaled version of the inductor current. the sample window time, t sample , is fixed and equal to 1/3 of the switching period, t sw as illustrated in figure 22. the sample current, at the end of the t sample , is proportional to the inductor current and held until the next switching period sample. the sample current is used for current balance, load-line regulation, and over-current protection. current sensing the ISL6247 supports inductor dcr sensing, mosfet r ds(on) sensing, or resistive current sensing techniques. the internal circuitry, shown in figures 23, 24, and 25, represents channel n of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the pwm3 and pwm4 pins, as described in the pwm operation section. inductor dcr sensing inductor windings have a characteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 23. the channel current i l , flowing through the inductor, will also pass through the dcr. equation 4 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 23. the voltage on the capacitor v c , can be shown to be proportional to the channel current i l , see equation 5. if the r-c network components are selected such that the rc time constant matches the inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr. the capacitor voltage v c , is then replicated across the sense resistor r isen . the current through the sense resistor is proportional to the inductor current. equation 6 shows the proportion between the channel current and the sensed current (i sen ) is driven by the value of the sense resistor chosen and the dcr of the inductor. t sample t sw 3 ---------- 1 3f sw ? ------------------ == (eq. 3) figure 22. sample and hold timing time pwm i l i sen sample current t sample switching period v l s () i l s l dcr + ? () ? = (eq. 4) v c s () sl ? dcr ------------- 1 + ?? ?? src ? 1 + () ------------------------------ - dcr i l ? ? = (eq. 5) figure 23. dcr sensing configuration i n - + isen-(n) sample & hold ISL6247 internal circuit v in isen+(n) pwm(n) isl6207 r isen(n) dcr l inductor r v out c out (ptc) - + v c (s) c i l - + v l (s) i sen i sen 1.3 i l dcr r isen ----------------- - ?? = (eq. 6) ISL6247
14 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly dcr varies with temperature, so a positive temperature coefficient (ptc) resistor should be selected for the sense resistor r isen . resistive sensing independent current sensing chip resistors in series with each output inductor can serve as the sense element, as shown in figure 24. this technique reduces overall converter efficiency due to the addition of a lossy element directly in the output path. the voltage across r isen is equivalent to the voltage drop across the current sensing chip resistor, r sense . the resulting current into the isen+ pin is proportional to the channel current i l . the isen current is sampled and held as described in the current sampling section. from figure 24, equation 7 derives i sen relative to the ratio between the current sensing chip resistor and the isen resistor to the channel current i l . one significant advantage of employing high quality current sensing chip resistors is their tight resistance tolerance over a wide operating temperature range. typical converter temperature ranges fall well within this range and remove the need for any temperature correction. mosfet r ds(on) sensing the controller can also sense the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 25. the amplifier is ground-reference by connecting the isen- input to the source of the lower mosfet. isen+ connects to the phase node through a resistor r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resulting current into the isen+ pin is proportional to the channel current i l . the isen current is sampled and held as described in the current sampling section. from figure 25, equation 8 derives i sen based on r ds(on) of the lower mosfet and the channel current i l . since mosfet r ds(on) increases with temperature, a ptc resistor should be chosen for r isen to compensate for this change. channel-current balance the sampled currents from each active channel are summed together and divided by the number of active channels. the resulting cycle average current i avg , provides a measure of the total load current demand on the converter during each switching cycle. channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse-width based on the error. intersil?s patented current-balance method is illustrated in figure 26, with error correction for channel 1 represented. in the figure, the cycle average current combines with the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. figure 24. sense resistor in series with inductors i n - + isen-(n) sample & hold ISL6247 internal circuit isen+(n) r isen(n) r sense l v out c out i l i sen i sen 1.3 i ? l r sense r isen ----------------------- = (eq. 7) figure 25. mosfet r ds(on) current-sensing circuit i n - + isen+(n) r isen sample & hold ISL6247 internal circuit external circuit v in n-channel mosfets - + i l r ds on () i l isen-(n) (ptc) i sen i sen 1.3 i l r ds on () r isen ---------------------- ? = (eq. 8) figure 26. channel-1 pwm function and current- balance adjustment n i avg i 4 * i 3 * i 2 - + + - + - f(s) pwm1 i 1 v comp sawtooth signal i er note: *channels 3 and 4 are optional. filter ISL6247
15 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly channel current balance is essential in realizing the thermal advantage of multi-phase operation. the heat generated in down converting is dissipated over multiple devices and a greater area. the designer avoids the complexity of driving multiple parallel mosfets, and the expense of using heat sinks and nonstandard magnetic materials. voltage regulation the output of the error amplifier v comp , is compared to the sawtooth waveform to modulate the pulse width of the pwm signals, as shown in figure 26. the pwm signals control the timing of the external intersil mosfet drivers and regulate the converter output voltage. the regulation level of the output voltage is determined by the mode of operation signaled by the processor, see the modes of operation section for more detail. feed-forward ramp compensation the ISL6247 features a rampadj pin for setting the pulse width modulator gain. the rampadj voltage is set by a resistor divider network from the battery voltage, as illustrated in figure 27. the rampadj voltage sets the peak-to-peak voltage of the ramp oscillator relative to the battery voltage. by feeding the battery voltage forward, the pulse width modulation gain, g mod , is independent of battery voltage, see equation 9. the ramp modulator gain is then set by the ratio of the maximum duty cycle, d max , to the amount of attenuation programmed by the resistor network on the rampadj pin. for imvp-5 applications, select r adj1 to be 8 times the value of r adj2 for an 1/9 attenuation of the battery voltage, resulting in a constant pulse width modulator gain of 6.0 over the entire range of battery voltage. reference voltage selection the reference voltage applied to the non-inverting input of the error amplifier is set by an internal multiplexer, as shown in figure 28. the multiplexer selects one of three modes of operation: active, deep sleep, or deeper sleep. depending on the mode selected, the multiplexer applies one of three user programmed voltage levels to the non-inverting input of the error amplifier. during mode changes, the voltage transition from one level to the next is managed by the soft- start circuitry. the output voltage transitions linearly from one level to the next. in active mode, a digital-to-analog converter (dac) generates a reference voltage based on the state of logic signals at pins vid0 through vid5. the dac decodes the 6- bit voltage identification codes (vid) into one of the discrete voltages shown in table 1. each vid pin is pulled to 0.95v by an internal 50 a current source and accepts open- collector, open-drain, or standard low-voltage ttl or cmos signals. deep sleep mode is entered when the dsen# signal from the processor is a logic low and drsen is low. the multiplexer switches the reference voltage to the voltage level externally programmed on the dsv pin. the soft-start circuitry linearly transitions the reference voltage from the active mode dac level to the new deep sleep mode dsv level. when the dsen# signal returns to a logic high, the reference voltage linearly transitions to the dac voltage programmed by the vid pins. the deeper sleep mode is entered when the drsen signal goes high and dsen# is low. the multiplexer then switches the reference voltage to the voltage level externally programmed on the drsv pin. the reference voltage transitions linearly due to the soft-start circuitry from the dsv level to the drsv level. when the drsen level returns low, the reference voltage is returned to the deep sleep mode dsv level. g mod d max v battery ? r adj2 r adj1 r adj2 + ------------------------------------------------- v battery ? ---------------------------------------------------------------------------------------- - 23 ? 1 9 -- - ---------- 6.0 === (eq. 9) figure 27. battery voltage feed-forward compensation r adj1 sawtooth v battery rampadj r adj2 signal - + pwm1 pwm sawtooth generator v comp ISL6247 internal circuitry figure 28. reference voltage multiplexer connections ISL6247 internal circuitry error amplifier v comp dac dsv drsv multiplexer - + v dsv v drsv vid5 vid4 vid3 vid2 vid1 vid d/a vid0 fb dsen# drsen reference voltage comp softstart soft ISL6247
16 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly output voltage feedback the output voltage sense points for the converter are connected to the vsen and vrtn inputs of an internal differential amplifier. by remote sensing the output voltage relative to its local ground, the differential amplifier eliminates voltage differences between the local ground of the controller and the remote sense point, providing a more accurate means of sensing output voltage. the remote- sense amplifier output v diff , is then tied through an external resistor, r fb , to the inverting input of the error amplifier; see the circuit illustration in figure 29. table 1. voltage identification codes vid4 vid3 vid2 vid1 vid0 vid5 vdac 0 1 0 1 0 0 0.8375v 0 1 0 0 1 1 0.8500v 0 1 0 0 1 0 0.8625v 0 1 0 0 0 1 0.8750v 0 1 0 0 0 0 0.8875v 0 0 1 1 1 1 0.9000v 0 0 1 1 1 0 0.9125v 0 0 1 1 0 1 0.9250v 0 0 1 1 0 0 0.9375v 0 0 1 0 1 1 0.9500v 0 0 1 0 1 0 0.9625v 0 0 1 0 0 1 0.975v0 0 0 1 0 0 0 0.9875v 0 0 0 1 1 1 1.0000v 0 0 0 1 1 0 1.0125v 0 0 0 1 0 1 1.0250v 0 0 0 1 0 0 1.0375v 0 0 0 0 1 1 1.0500v 0 0 0 0 1 0 1.0625v 0 0 0 0 0 1 1.0750v 0 0 0 0 0 0 1.0875v 1111 1 1 off 1111 1 0 off 1 1 1 1 0 1 1.1000v 1 1 1 1 0 0 1.1125v 1 1 1 0 1 1 1.1250v 1 1 1 0 1 0 1.1375v 1 1 1 0 0 1 1.1500v 1 1 1 0 0 0 1.1625v 1 1 0 1 1 1 1.1750v 1 1 0 1 1 0 1.1875v 1 1 0 1 0 1 1.2000v 1 1 0 1 0 0 1.2125v 1 1 0 0 1 1 1.2250v 1 1 0 0 1 0 1.2375v 1 1 0 0 0 1 1.2500v 1 1 0 0 0 0 1.2625v 1 0 1 1 1 1 1.2750v 1 0 1 1 1 0 1.2875v 1 0 1 1 0 1 1.3000v 1 0 1 1 0 0 1.3125v 1 0 1 0 1 1 1.3250v 1 0 1 0 1 0 1.3375v 1 0 1 0 0 1 1.3500v 1 0 1 0 0 0 1.3625v 1 0 0 1 1 1 1.3750v 1 0 0 1 1 0 1.3875v 1 0 0 1 0 1 1.4000v 1 0 0 1 0 0 1.4125v 1 0 0 0 1 1 1.4250v 1 0 0 0 1 0 1.4375v 1 0 0 0 0 1 1.4500v 1 0 0 0 0 0 1.4625v 0 1 1 1 1 1 1.4750v 0 1 1 1 1 0 1.4875v 0 1 1 1 0 1 1.5000v 0 1 1 1 0 0 1.5125v 0 1 1 0 1 1 1.5250v 0 1 1 0 1 0 1.5375v 0 1 1 0 0 1 1.5500v 0 1 1 0 0 0 1.5625v 0 1 0 1 1 1 1.5750v 0 1 0 1 1 0 1.5875v 0 1 0 1 0 1 1.6000v table 1. voltage identification codes vid4 vid3 vid2 vid1 vid0 vid5 vdac ISL6247
17 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly load-line regulation the ISL6247 meets the load-line requirements of intel imvp 5 processors by programming the output as a function of load current. the individual sample currents of all active channels i sen , are summed together and divided by four, see figure 19. the resulting droop current i droop , is proportional to the total output current of the converter and independent of the number of active channels. droop current is mirrored internally and carried to the inverting input of the error amplifier. the droop current is forced out the fb pin and creates a voltage drop across the feedback resistor r fb , proportional to the output current; see figure 29. the resulting steady-state value of output voltage droop is: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a function of load current is derived by combining equation 10 with the appropriate sample current expression defined by the current sense method employed. where v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the sense resistor in the isen line, and r fb is the feedback resistor. r x has a value of dcr, r ds(on) , or r sense, depending on the sensing method. i sen offset is defined in the section titled sample method offset resolution . reference offset typical microprocessor tolerance windows are centered around a nominal dac vid set point. implementing a load- line can require offsetting the output voltage above or below this nominal reference voltage. this allows centering of the load-line within the static specification window. the ISL6247 features an proprietary offset circuit which allows the user to select a single resistor to set a desired fixed offset, as shown in figure 30. negative offset below the reference voltage for imvp-5 applications, the tolerance window is centered below the nominal reference voltage, requiring a negative offset. by connecting r ofs to vcc, a negative output offset is programmed. amplifier a 2 forces the voltage on ofs to (vcc - 2v), and this sets the current i 2 flowing through r ofs (per equation 12), and i 2 flows out the fb pin. this current creates a voltage across r fb , which causes a regulated output voltage that is v ofs below the reference voltage. v droop n i ( 1 ) = i sen 1 4 -- - r fb ?? = (eq. 10) figure 29. inverting input connections i droop external circuit ISL6247 internal circuit comp c c r c r fb fb vdiff vsen vrtn - + v droop v ofs error - + v out remote sense differential remote-sense amplifier v comp gnd points i ofs ofs r ofs - + v diff reference voltage amplifier gnd or vcc offset v out v ref v ofs ? 1.3 i out 4 -------------- - r x r isen ------------------- - ? ? ? i sen offset + ? ? ? ? rfb ? ? = (eq. 11) figure 30. reference offset circuitry fb vdiff error amplifier - + - + - + r fb - + v ofs ofs vcc r ofs vcc or gnd gnd q 1 q 2 +2.0v +0.5v a 1 a 2 i 1 i 2 - + v ofs +5v v ref i 2 2v r ofs --------------- - v ofs r fb ------------------ == (eq. 12) ISL6247
18 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly rearranging equation 12, select the resistor value based on the voltage offset desired using equation 13. positive offset above the reference voltage for a positive offset of the output voltage, connect the offset resistor, r ofs , to ground. by connecting the external resistor to ground, amplifier a 1 forces the voltage on ofs to +0.5v. this results in a known current i 1 , flowing through r ofs (see equation 14) which is pulled out of the fb pin. this creates an offset voltage v ofs , across r fb , as shown in figure 30, reducing the voltage at the inverting input of the error amplifier relative to the magnitude of i 1 . using the relationship between the current set by r ofs and the voltage offset created by this current through r fb , equation 15 results for selection of r ofs . the integrating compensation network (r c and c c ), shown in figure 29, assures that the steady-state error in the output voltage is minimized. the ISL6247 system accuracy, specified in the electrical specification table , includes all variations in current sources, amplifiers and the dac reference over temperature. sample method offset resolution a sample current offset results from the timing scheme of the sampling method, see the current sampling section for more detail. the sample current translates to a droop current offset derived in equation 16. adjust the r ofs value accordingly to account for this offset. where v out is the output voltage, f sw is the switching frequency, and d is the duty cycle. switching frequency resistor r fs , connected between the fs pin and ground, sets the frequency of the internal oscillator. figure 31 provides a graph of oscillator frequency vs. r fs . the maximum recommended channel frequency is 1.0mhz. during the selection process, attention should be paid to the mosfet loss calculations which establish the upper limit for the switching frequency. the requirements for fast-transient response and small output voltage ripple establish the lower limit. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. once a switching frequency value is chosen, use equation 17 to select the value of r fs ( ? ), where f sw is in hertz. operation initialization converter operation is initialized with a soft-start interval. once the output voltage is within the proper window of operation, the pgood output changes state to update an external system monitor. enable and disable the pwm outputs are held in a high-impedance state, which insures the isl6207 drivers remain off while in shutdown mode. three separate input conditions must be met before the ISL6247 is released from shutdown mode (figure 32). first, the internal power-on reset circuit (por) prevents the ISL6247 from starting before the bias voltage at vcc reaches the por-rising threshold, as defined in electrical specifications . the por-rising threshold is high enough to guarantee that all parts of the controller can perform their functions properly. built-in hysteresis between the rising and falling thresholds insures that once enabled, the controller will not inadvertently turn off unless the bias voltage drops substantially. when vcc is below the por-rising threshold, the pwm outputs are held in a high-impedance state to assure the drivers remain off. r ofs 2v r fb ? v ofs ----------------------- = (eq. 13) i 1 0.5v r ofs --------------- - v ofs r fb --------------- == (eq. 14) r ofs 0.5v r fb ? v ofs ---------------------------- = (eq. 15) i sen offset 1.3 v out lfws ? ----------------- 1 6 -- - d 2 -- - ? r x r isen ---------------- - ?? ? = (eq. 16) figure 31. r fs vs switching frequency 100 1000 switching frequency (khz) 10 100 1000 r fs (k ? ) r fs 10 11.15 1.13 f sw () log ? [] = (eq. 17) ISL6247
19 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly after power on, the ISL6247 remains in shut-down mode until the voltage at the enable input enll, rises above the enable threshold. once this threshold is exceeded, the controller will start up, given all the enable inputs are in the proper state. the 111111 and 011111 vid codes are reserved as signals to the controller that no load is present. the controller will latch and enter shutdown mode after receiving this code. to enable the controller, vcc must be greater than the por threshold, the voltage on enll must be greater than the enable threshold, and vid cannot be equal to 111111 or 011111. once these conditions are true, the controller immediately initiates a soft-start sequence. soft-start interval once the ISL6247 is enabled, a capacitor, c soft , must be present between the soft pin and ground as shown in figure 33. two internal current sources, which flow out the soft pin, charge the capacitor at two distinct rates. the voltage on the soft pin provides a slow rising reference voltage to the non-inverting input of the error amplifier. a controlled rise in output voltage avoids encountering an over-current condition, described in fault monitoring and protection , by slowly charging the discharged output capacitors. in figure 34, a soft-start interval is illustrated from start to finish. the first interval, from t 1 to t 2 , is a wait period for the soft-start circuitry to initialize. equation 18 shows the wait period in terms of switching frequency. once the wait period has expired, the second interval, from t 2 to t 4 , begins. switch s1 closes and a 25 a current source begins charging the c soft capacitor. simultaneously, a current i ramp begins flowing out the fb pin. i ramp linearly ramps from 140 to 0 a over the same time span v soft rises from 0 to 0.5v. during the sub-interval t 2 to t 3 , the offset voltage across r fb , due to i ramp , is greater than v soft . once v soft exceeds this offset, the first pwm pulses are produced and the output voltage linearly slews to 0.5v. second interval duration is based on the charging time of c soft to 0.5v; see equation 19. the final interval of the soft-start interval, t 4 to t 5 , begins with switch s2 closing. the second current source adds to the first, for a total charging current of 500 a. the i ramp current has expired and the output voltage follows the voltage rise on c soft . when v soft reaches the vid programmed reference voltage, switches s1 and s2 open. equation 20 defines the third interval of the soft-start interval. figure 32. enable and disable inputs - + 0.6v external conditions ISL6247 enll vcc +5v por circuit enable comparator dac vid5 vid4 vid3 vid2 vid1 vid d/a vid0 figure 33. soft-start slew rate control c soft error v soft amplifier - + 25 a 475 a s1 s2 - + i ramp fb soft r fb to vdiff v ref t 12 ? 32 1 f sw ---------- ? = (eq. 18) figure 34. soft-start interval waveforms time 0v 0v vcore, 500mv/div soft, 500mv/div 0v pgood, 5v/div enll, 2v/div 0v t 1 t 2 t 3 t 4 t 5 t 24 ? 0.5v () c soft () 25 a ------------------------------------------ = (eq. 19) t 45 ? vid 0.5v ? () c soft () 500 a ----------------------------------------------------------- = (eq. 20) ISL6247
20 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly the total soft-start interval is the sum of equations 18, 19, 20. selection of the soft-start capacitor is driven by the maximum slew rate in (v/s) required by the imvp-5 specification, addressed in modes of operation . once the output voltage rises above 90% of the vid setting, the power good signal (pgood) changes to a high state, as shown in figure 34. once high, pgood will only transition low when the controller is disabled or a fault condition is detected. see the power good signal sub-section of the fault monitoring and protection section for additional information on the capability of this pin. modes of operation the ISL6247 supports power state optimization transitions per the imvp-5 specification for fixed mobile solutions (fms). three distinct modes of operation, signaled by the processor, are determined by the state of the stp_cpu# and dprslpvr signals. these inputs connect to dsen# and drsen respectively and cycle the controller through active, deep sleep, and deeper sleep modes as shown in figure 35. active mode when dsen# is high and drsen is low, active mode is selected by the processor. the ISL6247 determines the output voltage from the processor controlled vid codes. the corresponding dac voltage provides the reference voltage, v ref , to the error amplifier and consequently the converter output voltage. the ISL6247 supports enhanced intel speedstep transitions, designed to maximize processor performance in notebook systems. when the notebook power source is changed from an ac outlet to a battery, the processor drops to a lower operation voltage. the processor communicates this change by adjusting the vid codes. the ISL6247 detects the vid change and immediately begins slewing the output voltage to the new setting. figure 36 illustrates a vid change in either direction. the slew rate in either direction, sr1 and sr2, is equivalent and set by the soft capacitor. slew rate selection the imvp-5 timing requirements define the minimum slew rate during a set vid change. referencing figure 33, the size of the soft capacitor sets the maximum slew rate of the ISL6247. equation 21 outlines how to select the capacitor based on the slew rate (v/s) targeted. take into account the capacitor tolerance when sizing c soft to prevent violation of the imvp-5 minimum timing specification, where slewrate is defined in the imvp-v specification. deep sleep mode while in active mode, the controller monitors the state of the mode selection pins. when dsen# goes low, the ISL6247 enters deep sleep mode. an internal multiplexer changes the reference voltage to the deep sleep voltage level externally set on the dsv pin. the converter immediately begins slewing the output voltage to the deep sleep voltage. the output voltage slew rate into and out of deep sleep mode (sr1 and sr2) is equivalent to the speedstep transition. active to deep sleep mode transition and vice versa is shown in figure 37. figure 35. power optimization states active mode deep sleep mode deeper sleep mode dsen# = 1 dsen# = 0 dsen# = 0 dsen# = 0 drsen = 1 drsen = 0 drsen = 0 drsen = 0 stp_cpu# = dsen# drpslpvr = drsen dsen# = 1 drsen = 1 figure 36. speedstep output voltage change vid[0.5] v out current vid new vid code pgood current output new output level high sr1 sr2 code level c soft soft slewcurrent slewrate -------------------------------------------------- = (eq. 21) figure 37. deep sleep state timing dsen# v out pgood high drsen low vid[0.5] current vid code new vid code current output new output level sr1 sr2 level ISL6247
21 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly figure 38 illustrates the multiplexing between the three modes of operation and the reference voltage. a resistor divider from the ocset pin is shown for selection of the deep sleep voltage. using this configuration, the dsv level is proportional to the dac, since the ocset voltage is the dac voltage. deeper sleep mode once in deep sleep mode, a high on drsen signals entry into deeper sleep mode. the controller immediately switches to single-phase operation and the multiplexer makes the reference voltage the deeper sleep voltage level, drsv. current feedback from the previously active channels and the vid inputs are ignored by the controller while in this mode. the soft slew current is reduced during the transition into deeper sleep mode. the voltage slew rate from dsv to drsv is slowed as a result; see figure 39. the controller exits deeper sleep mode when drsen returns low. the controller enables the previously active channels and returns the reference voltage to the dsv level. the soft slew current returns to the previous level of 500 a to provide the required swift re-entry into deep sleep mode. the state diagram in figure 35 shows a direct path from active mode to deeper sleep highlighted in red. the path is not a valid imvp-5 state transition and will not be entered by processor controlled enable lines. fault monitoring and protection the ISL6247 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. power good signal the power good pin (pgood) is an open-drain logic output which indicates when the converter is operating within the imvp-5 specifications and externally set over-current threshold. the schematic in figure 40 outlines the interaction between the fault monitors and the pgood state. pgood pulls low during shutdown and remains low when the controller is enabled, as described in enable and disable . during a soft-start interval, pgood releases high once the output voltage passes through the under-voltage (uv) rising threshold. drsen figure 38. reference voltage selection dsv to ocset r 1 r 2 dsen# stp_cpu# mux dac drsv to fcs r 4 dprslpvr r 3 v ref soft softstart c soft 0.75v figure 39. deeper sleep state timing drsen pgood high dsen# low vid[0.5] current vid code new vid code v out dsv dsv drsv sr1 sr2 figure 40. power good detection inputs - + v ref vdiff - + - + ov oc uv pgood - + en enll i ocset repeated for each channel i sen v dac + 0.2v rising 90% 0.6v cycle 32 count clock falling 86% por circuit vcc latch cycle 8 count clock ISL6247
22 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly pgood transitions low immediately following enll descending below the enable threshold, vcc dropping below the falling por threshold, or a speedstep transition to one of the no-cpu codes (011111 or 111111). pgood will return high following enll rising above the enable threshold, vcc rising above the por rising threshold. pgood pulls low and is latched when an under-voltage, over-voltage or over-current condition is detected as illustrated in figure 40. once latched, pgood will remain low until vcc is cycled below the por falling threshold or enll is toggled below 0.6v. under-voltage protection the under-voltage rising threshold is 90% of the reference voltage and the falling threshold is 86% of the reference voltage. during soft-start, the slowly rising vdiff eventually exceeds the rising threshold and pgood releases high. if vdiff drops below the falling threshold, see figure 41, a counter begins tallying switching cycles. once the counter reaches eight, the active pwm signals are placed in a high- impedance state and pgood pulls low. if vdiff rises above the uv rising threshold, within the 8 cycle window, the counter counts down and converter operation is not interrupted. over-voltage protection if vdiff exceeds the dac voltage by 200mv, the over- voltage comparator goes high. the change in state of the over-voltage signal prompts pgood to go low indicating a fault condition exists. an internal reset latch is simultaneously set to prevent a change in state of the ov signal from resetting the fault protection actions. the protective actions begin with all pwm outputs commanded low. the isl6207 drivers turn on the lower mosfets shunting the output to ground. this protection action prevents any further increase in output voltage. once vdiff falls below the dac over-voltage threshold, all pwm signals enter a high-impedance state. this prevents charge dumping of the output capacitors back through the output inductors and lower mosfets which would cause a negative output voltage. this architecture eliminates the need of a high-current schottky diode on the output. if external fault conditions cause the output voltage to rise above the over-voltage threshold again, the ISL6247 commands all pwm outputs low once again. the ISL6247 continues to protect the load in this fashion as long as the over-voltage repeats. the reset latch is cleared by cycling enll below the enable threshold or vcc below the por falling threshold. over-current protection each active channel is protected from a sustained over- current condition. the ISL6247 takes advantage of the proportionality between the load current and the sensed current to continuously compare the channel sample current, i sen , with an externally programmed over-current trip threshold, i ocset . if any of the channel sample currents exceed i ocset , an internal 32-count up-down counter increments during each consecutive switching cycle. if a few switching cycles occur between fault detections, the counter will count down but not below zero. when the counter reaches 32, the comparator triggers the converter to shutdown and sets an internal latch preventing continued pwm operation. all pwm signals are placed in a high- impedance state commanding the isl6207 drivers to turn off both upper and lower mosfets. the latch is cleared by cycling enll below the enable threshold or vcc below the por falling threshold. ocset resistor selection the programmable over-current trip threshold, illustrated in figure 42, is set by the current flowing through the ocset pin. the ocset pin is held at the dac voltage with a resistor to ground allowing for selection of i ocset . the over-current trip threshold is set relative to the scaled full load channel sense current, typically 50 a. in equation 22,the ratio k is set by the ratio of converter trip current, i trip (a), to the converter full load output current, i fl (a). equation 23 shows the selection criteria for r ocset . do not add external capacitance to this pin. figure 41. under-voltage protection waveforms time 0v vcore, 50mv/div 1.5v pgood, 5v/div pwm1, 5v/div 0v t 1 t 2 uv falling i ocset ki sen fl i sen offset + ?? ?? i trip i fl -------------- - i sen fl i sen offset + ?? ?? == (eq. 22) r ocset v ocset i ocset ----------------------- v dac ki sen fl i sen offset + ?? ?? ------------------------------------------------------------------------ == (eq. 23) ISL6247
23 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly voltage regulator thermal throttling lntel imvp-5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. the ISL6247 features a thermal monitor which senses the voltage change across an externally placed negative temperature coefficient (ntc) resistor network; see figure 43. proper selection and placement of the ntc thermistor allows for detection of a designated temperature rise by the voltage regulator. when the temperature of the ntc thermistor reaches the prescribed level, the voltage at the ntc pin ideally is 0.5v. the internal comparator goes high turning on the open-drain vr-tt# pull-down. vr-tt# is connected directly to the active-low processor i/o pin named prochot#. the processor?s thermal control circuit (tcc) is activated and thermal throttling is initiated. this function is intended to prevent catastrophic overheating of the imvp-5 regulator components and printed wiring board (pwb). thermal throttling by the processor degrades system performance and should not occur below normal thermal design power levels. ntc resistor network selection of the ntc thermistor is simplified with the addition of a second standard resistor in series, as shown in figure 43, or in parallel, or an ntc thermistor alone. the series or parallel approach widens the standard value choices for the ntc thermistor. the ntc resistor network equivalent resistance, r net , must be equal to 12.5k ? at the desired fault temperature. this value is set by the comparator detection threshold (0.5v) and the 40 a current source which flows out the ntc pin. the ntc thermistor resistance at room temperature, r 25 , and a table of resistance ratios relative to r 25 over the operating temperature range of the thermistor are provided by most manufacturers. from the thermistor resistance ratio table, follow the previously determined t fault value across to the material tolerance type selected and determine the resistance ratio k fault at that temperature. r fault represents the resistance of the ntc thermistor at the selected fault temperature. equation 24 outlines that the ratio between r fault to r 25 must be less than one. the standard resistor value to place in series with the selected ntc thermistor is derived in equation 25. application information component selection guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. it is assumed the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of material, and example board layouts specifically for imvp-5 applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. generally speaking, the most economical solutions are those in which each phase handles between 15 and 20a. in cases where board space is the limiting constraint, current can be pushed as high as 30a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat- dissipating surfaces. lntel imvp-5 platforms require between 68a to 80a, which suggests converter designs with 3 to 4 channel operation. mosfet selection and considerations the choice of mosfets depends on the current each mosfet will be required to conduct; the switching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. the power dissipation includes two loss components: conduction loss and switching loss. these losses are distributed between upper and lower mosfets according to duty cycle of the converter. refer to the p upper and p lower equations below. the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfets have significant switching losses, since the lower devices turn on and off into near zero voltage. figure 42. over-current circuitry - + oc i ocset repeat for each channel i sen cycle 32 count clock ocset protection circuitry r ocset figure 43. thermal monitor circuitry 0.5v ntc r - + r net - + 40 a vr-tt# internal to ISL6247 r ntc k fault r fault r 25 ---------------------- 1 < = (eq. 24) rr net r fault ? 12.5k ? r 25 k fault ? () ? == (eq. 25) ISL6247
24 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly the following equations assume linear voltage-current transitions and do not model power loss due to the reverse- recovery of the lower mosfets body diode. the gate-charge losses are dissipated in the isl6207 drivers and do not heat the mosfets; however, large gate-charge increases the switching time, t sw , which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature, at high ambient temperature, by calculating the temperature rise according to package thermal- resistance specifications. input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a two-phase design, use figure 44 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the combined peak-to-peak inductor current (i c,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figures 45 and 46 provide the same input rms current information for three and four phase designs respectively. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. output inductor selection the output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient. in a multiphase converter topology, the ripple current of one active channel partially cancels with the other active channels to reduce the overall ripple current. the reduction in total output ripple current results in lower overall output voltage ripple. the inductor selected for the power channels determines the channel ripple current. increasing the value of inductance p lower i o 2 r ds on () v in v out ? () ?? v in ------------------------------------------------------------------------------ - = (eq. 26) p upper i o 2 r ds on () v out ?? v in --------------------------------------------------------- - i o v in t sw f sw ?? ? 2 ---------------------------------------------------- + = figure 44. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms / i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in / v o ) i c,pp = 0 i c,pp = 0.5 i o i c,pp = 0.75 i o figure 45. normalized input-capacitor rms current for 3-phase converter duty cycle (v in / v o ) 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms / i o ) 0.3 0.1 0 0.2 i c,pp = 0 i c,pp = 0.25 i o i c,pp = 0.5 i o i c,pp = 0.75 i o figure 46. normalized input-capacitor rms current for 4-phase converter input-capacitor current (i rms / i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in / v o ) 0.3 0.1 0 0.2 i c,pp = 0 i c,pp = 0.25 i o i c,pp = 0.5 i o i c,pp = 0.75 i o ISL6247
25 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly reduces the total output ripple current and total output voltage ripple. however, increasing the inductance value will slow the converter response time to a load transient. one of the parameters limiting the converter response time to a load transient is the time required to slew the inductor current from its initial current level to the transient current level. during this interval, the difference between the two levels must be supplied by the output capacitance. minimizing the response time can minimize the output capacitance required.the channel ripple current is approximated in equation 27. the total output ripple current can be determined from the curves in figure 47. the curves are a function of the duty cycle and number of active channels, normalized to the parameter k norm at zero duty cycle. where l is the channel inductor value. find the intersection of the active channel curve and duty cycle for your particular application. find the corresponding ripple current multiplier from the y-axis. multiply the k cm value, found from figure 47, by the normalization factor k norm, calculated per equation 28. the result is the total output ripple current for the given application as shown in equation 29. output capacitor selection in high-speed converters, the output capacitor bank is usually the most costly part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, equivalent series resistance (esr), and equivalent series inductance (esl). typical output capacitor solutions are made up of a mixture of low-capacitance ceramics along with high-capacitance aluminum electrolytic or special polymer bulk capacitors. at the beginning of a load transient, the ceramic capacitors supply the initial transient current and slow the rate-of- change seen by the bulk capacitors. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the bulk capacitor esr increases linearly until the load current reaches it final value. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by the amount derived in equation 30. the filter capacitor must have sufficiently low esl and esr such that ? v < ? v max . intel imvp-5 specifications outline the total number and type of output capacitors to support the transient slew rates produced by the processor. layout considerations careful printed circuit board (pcb) layout is critical in high- frequency switching converter design. with components switching at greater than 200khz, the resulting current transitions from one device to another induce voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, lead to device over-voltage stress, radiate noise into sensitive nodes, and increase thermal stress on critical components. careful component placement and pcb layout minimizes the voltage spikes in the converter. the following multi-layer printed circuit board layout strategies minimize the impact of board parasitics on converter performance and optimize the heat-dissipating capabilities of the printed-circuit board. this section highlights some important practices which should not be overlooked during the layout process. ? i channel v in v out ? lf sw ? ------------------------------- - v out v in --------------- - ? = (eq. 27) k norm v out lf sw ? ------------------ = (eq. 28) ? i total k norm k cm ? = (eq. 29) 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 duty cycle (v o /v in ) single channel 3 channel 4 channel figure 47. ripple current vs duty cycle current multiplier, k cm 2 channel ? vesl di dt ---- - ? esr ? i ? + = (eq. 30) ISL6247
26 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly component placement determine the total implementation area and orient the critical switching components first. symmetry is very important in multiphase converter placement and the switching components dictate how the available space is filled. the switching components carry large amounts of energy and tend to generate high levels of noise. addressing these issues during component placement allows for reduction of potential switching noise magnitude and radiation into critical nodes. each power channel of the multiphase converter is made up of an output inductor, upper and lower mosfets, and isl6207 driver. orient the mosfets and inductor first to set the dimension of the resulting phase plane. keeping the components in tight proximity will help reduce parasitic impedances once the components are routed together. figure 48 illustrates the placement and connection of critical components for one power channel of a converter. place the isl6207 driver in close proximity to the phase plane and the gates of the mosfets. keep enough open space available around the driver for placement of the boot capacitor, c boot and bypass capacitor. duplicate the resulting power channel placement as required in the given implementation area. in figure 48, c in and c out represent numerous physical capacitors. position one high-frequency ceramic input capacitor next to each upper mosfet drain. align the body of the capacitor such that the ground connection is coincident with the source of the lower mosfet. place the bulk input capacitors as close to the upper mosfet drain(s) as dictated by the component size and dimensions. long distances between input capacitors and mosfets drains results in too much trace inductance and a reduction in capacitor performance. locate the output capacitors between the inductors and the load, while keeping them in close proximity around the microprocessor socket. care should be taken not to add inductance in the circuit board traces that could cancel the usefulness of the low inductance components. the ISL6247 can be placed off to one side or centered relative to the individual channel switching components. routing of sense lines and pwm signals will guide final placement. critical small signal components to place close to the controller include the feedback resistor r fb , frequency select resistor r fs , offset resistor r ofs , over- current select resistor r ocset , feed-forward ramp adjustment resistors r adj1 and r adj2 , and slew rate capacitor c soft , deep and deeper sleep voltage divider resistors, and compensation components r c and c c . because the remote sense traces for vsen and vrtn may be long and routed close to switching nodes, a 1.0 f ceramic decoupling capacitor can be located between vsen and rtn pins of the package. the dcr sensing components, r and c, must be placed in parallel with the inductor. place the ptc r isen resistor just off the inductor pads to allow it to track the inductor temperature properly. the further away the ptc is placed from the inductor, the weaker the temperature correlation between the inductor and ptc. place the ntc thermistor, r ntc , near a critical switching component which dissipates heat into the board. the standard 1% resistor, r, in the ntc network should be placed close to the ISL6247. bypass capacitors, c bp , supply critical bypassing current for the ISL6247 and isl6207 drivers bias supplies and must be placed next to their respective pins. stray trace parasitics will reduce their effectiveness, so keep the distance between the vcc bias supply pad and capacitor pad to a minimum. plane allocation pcb designers typically have a set number of planes available for a converter design. dedicate one solid layer, usually an internal layer if available, for a ground plane. the ground plane should be split into two separate planes connected together at one point. the main power ground plane which supports the high-currents demanded by the load and a noise sensitive analog ground plane. connecting the two planes at one point minimizes the noise injection from the high-frequency current components in the power ground plane into the sensitive circuits grounded to the analog ground plane, or sometimes referred to as the signal ground plane. another common practice is the star ground in which all sensitive components connect together at one point and then to the power ground. this approach has the same effect as separating the power- and analog-ground planes, but is not always practical depending on the board complexity. one additional solid layer is dedicated as a power plane and broken into smaller islands of common voltage. the remaining pcb layers are used for small signal routing and additional power or ground islands as required. signal routing if the power channel component placement guidelines are followed, stray inductance in the switch current path created by the copper filled phase plane is minimized. stray inductance in these high-current paths induce large noise voltages that couple into sensitive circuitry. by keeping the phase plane small, the magnitude of the potential spikes is minimized. duplicate the power channel component placement and layout for each phase. the isl6207 gate trace impedance must be kept low to reduce switching loss, lower switching component and board temperature, and lower output voltage ripple. routing the driver and mosfets on the same layer with short, wide traces helps reduce both parasitic resistance and inductance. size the driver gate traces to carry at least 4a of current, recommended trace width is 4mm. ISL6247
27 int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly sensitive signals should be routed on different layers or some distance away from the phase planes on the same layer. crosstalk due to switching noise is reduced into these lines by isolating the routing path away from the phase planes. layout the phase planes on one layer, usually the top or bottom layer, and route the isen, vsen, vrtn, and ntc traces on another layer remaining. r ntc r v out +5v via connection to ground plane island on power plane layer island on circuit plane layer l o1 c out c in v battery key vcc use individual metal runs comp ISL6247 pwm r fb r c c bp fb vdiff isen+ r isen(n) isl6207 c boot c bp c c vcc soft boot isolate output stages for each channel to help figure 48. printed circuit board power planes and islands l parasitic phase ugate lgate pwm gnd r adj1 r adj2 c r isen- gnd ofs r ofs vrtn vsen fs ntc rampadj +5v phase r fs c soft 1.0 f via connection to analog ground island ISL6247
28 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com int er sil confid e nt ial f o r in t el im v p -5 l ic ens ees on ly ISL6247 quad flat no-lead plastic package (qfn) l40.6x6 40 lead quad flat no-lead plastic package (compliant to jedec mo-220vjjd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 6.00 bsc - d1 5.75 bsc 9 d2 3.95 4.10 4.25 7, 8 e 6.00 bsc - e1 5.75 bsc 9 e2 3.95 4.10 4.25 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n402 nd 10 3 ne 10 3 p- -0.609 --129 rev. 1 10/02 bsc = basic lead spac ing between centers notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

▲Up To Search▲

Price & Availability of ISL6247

	To Download ISL6247 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .